In the last posts I focused on implementation of square root algorithm. I wrote codes for iterative and piplined versions. Today I wanted to compare them. Additionally for comparison I added two square root IPs (ALTSQRT) generated by Quartus. Primary goal is to answer to the following question: is it better to use IP core or write own square root calculator? I focused only on the used resources.
Read More »Square Root. Part 3 – summary.In a previous post I implemented an iterative version of a square root algorithm described in the article: “A New Non-Restoring Square Root Algorithm and Its VLSI Implementations” written by Yamin Li and Wanming Chu. Here I present the pipelined version from the same article.
Read More »Square Root. Part 2 – pipelined version.Recently I had to implement square root algorithm in an FPGA. During research I found quite old, but interesting article: “A New Non-Restoring Square Root Algorithm and Its VLSI Implementations” written by Yamin Li and Wanming Chu. For educational purposes I decided to implement presented algoritm in VHDL.
Read More »Square Root. Part 1 – iterative version.Array, a collection of values of the same type, is very useful representation of data in VHDL. It is helpful during creating memory blocks (FIFOs, shift registers, RAM, ROM) or in designs where exist duplicated data flows, pipes or blocks (many ADC channels, filters etc). They can be used in synchronous designs as well as in combinational. But using it in combinational parts, sometimes for specific solution, it is very important to be aware how the code will be interpreted and synthesized.
To use the array object in the code, we need to do following steps:
I don’t like magic numbers or redundant variables in the code. They make it unclear and unreadable. Fortunately, VHDL gives many various options to eliminate such parts. One of them are predefined attributes. VHDL delivers many groups of attributes, which are useful in many situations. Some of them work only with signals, other with specific data types etc., but in general, rule of using an attribute is always the same:
object‘attribute
Read More »Attribute LENGTHThis is the last part about creating almost automatic testbench for Moving Average Filter. In the previous post I presented blocks for reading and writing. Now it is time to connect all blocks to each other in the main testbench. Testbench contains three blocks:
Testbench additionally contains clock generation and other processes which drive control and testbench signals.
Read More »Developing design: moving average filter. Part 7 (last) – testbench.I had a break in developing filter (last part is here), but before doing next steps, I had to make a short introduction to working with files in VHDL. You can read about it here, here and here. Now I am going to use that knowledge and move on with the filter. In the last part I implemented the filter in Octave, generated test vectors, sent them through the filter and wrote all data to files.
Now it is time to start building testbench, where the filter could be easily and automatically verified with different test vectors. To achieve it, testbench has to read data from a file and pass it to the filter and then, write output values from the filter to another file.
Read More »Developing design: moving average filter. Part 6 – reading and writing to the files.Before you read that post, I encourage you to go through my two previous posts (here and here), which are about working with files. They describe basic approach and explain why that method is not recommended. Instead of this, in the following post I am proposing more standard, popular and convenient way to work with files in the VHDL.
TextIO is a package created to simplify working with files. It works in the same way on every operating system with almost every type available in the VHDL.
Read More »TextIOIn previous post I explained in 5 steps how looks communication with files in VHDL. I presented some basic codes, which do simple write/read operations. Today I wanted to focus on that codes. If anyone tried to simulate them probably noticed that result are different from expectations. Below hopefully you will find an answer why…
Read More »Files – data representation mismatchVHDL provides mechanism to work with files. This feature is useful, when there is a need to store some data like test vectors, parameters or results of the simulation. Way of working with files in VHDL is very similar to other languages. File is treated as an object. It can be created in an architecture body, process or subprograms. To properly work with files, following steps should be done:
1. Define type of a file
2. Declare object of the defined file type
3. Open the file
4. Perform write/read operations
5. Close the file