June 2016

Entity declaration

As mentioned in previous post, systems are created using one or more entities. In case of many entities in the project, the uppermost level of it, is top-level entity. To connect modules with other modules or external world, ports and signals are used (Fig. 1). Main role of entity declaration is to define these ports – their names, types, width and direction. Basically entity declaration shows how module is seen by other modules. It describes the external view of the module with no information what is inside. Additionally entity declaration includes name of the entity and other parameters (constants, types, asserts, function etc).

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About VHDL…

All about history, advantages and disadvantages of VHDL you can find on wiki or other similar sites, so there is no point in copying this information. Here I would like only to list main features of this language:

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