All about history, advantages and disadvantages of VHDL you can find on wiki or other similar sites, so there is no point in copying this information. Here I would like only to list main features of this language:
- VHDL originally was developed to describe behavior and structure of logic circuits.
- VHDL can be used to model a wide range of digital systems from very simple gate to more complex designs (i.e. digital filters or microprocessors).
- VHDL supports three basic description styles: structural, behavioral and dataflow.
- VHDL allows to express not only sequential but also concurrent behavior of digital system.
- Only small part of VHDL can be synthesized and then realized in hardware.
- Designs can be verified by testbenches also written in VHDL. There in no need to learn another language for simulation.
- VHDL allows to use of explicit time delays.
- VHDL is a strongly typed language.
The basic block in VHDL is called a design entity (sometimes module, component). VHDL design can contain only one or more entities. Entity from the external point of view can be treated as black box which has some inputs, some outputs and performs some operations.
To describe the design entity in VHDL, two parts related to each other must be specified: entity declaration and architecture body. Details about entity declaration and architecture body you will find in next posts.