Entity declaration

As mentioned in previous post, systems are created using one or more entities. In case of many entities in the project, the uppermost level of it, is top-level entity. To connect modules with other modules or external world, ports and signals are used (Fig. 1). Main role of entity declaration is to define these ports – their names, types, width and direction. Basically entity declaration shows how module is seen by other modules. It describes the external view of the module with no information what is inside. Additionally entity declaration includes name of the entity and other parameters (constants, types, asserts, function etc).

Fig. 1


Now it is time to write simple code – entity declaration for 2-input OR gate:

entity OrGate is
  port (	
    a	:in std_logic;
    b	:in std_logic;
    y	:out std_logic
end OrGate;


Line 1. – Entity name should be simple and must be unique. Sometimes I hear that name of the entity and name of the file in which the entity is described should be the same. This is not true. Names of file and entity can be different. You can place as many entity declarations in one file as you want.
Line 2. – this line informs that declarations of the input/output signals are starting.
Line 3. to 6. – declaration of port:

port_name : direction type;

In this example is used basic type – std_logic. You can see two input ports: a and b and one output port: y.

Line 7. to 8. – end of declaration. You can do it in three different ways:

  • end entity;
  • end entity_name;
  • end entity entity_name;

Here was presented basic information about entity declaration. Next I will write about architecture body. Then you should be able to write your first component in VHDL and simulate it.

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All source codes used in that post you can find on gitlab.com.

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