Very often is necessary to detect edges of signals in designs. It can be helpful during developing communication interfaces, filters, sequential events. It seems that writing this module is easy, but as always designer should be careful. He has to remember, that his VHDL code will be synthesized to hardware, so he should keep in mind what structure will be created and how tools will understand his intentions.
Read More »Edge detectorIn previous posts I showed, how to build OR gate. This was an example of combinational logic. If you look at the code, you will see, that output depends only on present inputs and changes as fast as possible after modifying them. Though you have to know how to build combinational logic and how it works, you won’t create any bigger design only with that. To store data or pipeline the calculations, you have to create synchronous logic, dependent on a clock.
Read More »Registers (synchronous designs)Having entity declaration and body architecture only one thing is still to do before compilation. I have to inform compiler which libraries are needed to analyze the design. Therefore, before entity declaration I inserted name of the library and package which will be used. This is ieee library and package std_logic_1164 (package, which contains declarations of basic types used in the design).
Read More »Testbench and SimulationIn previous post I presented entity declaration and gave simple example. Now it is time for second part – architecture body. Without this part, you won’t be able to create any module in VHDL.
Entity declaration gives information how module is connected with external world. Architecture body gives information what is inside of the module. It specifies relationship between input and output ports. In other words it specifies behavior of the module.
You should know there are three different modeling styles which allow to describe architecture body:
Sometimes some people add the fourth style – mixed, which is combination of three mentioned styles.
Read More »Architecture body