In previous post I presented entity declaration and gave simple example. Now it is time for second part – architecture body. Without this part, you won’t be able to create any module in VHDL.
Entity declaration gives information how module is connected with external world. Architecture body gives information what is inside of the module. It specifies relationship between input and output ports. In other words it specifies behavior of the module.
You should know there are three different modeling styles which allow to describe architecture body:
- structural description
- behavioral description
- dataflow description
Sometimes some people add the fourth style – mixed, which is combination of three mentioned styles.
Architecture body can be split into two parts. Fist part (before the keyword begin) is declarative part and the second (after the keyword begin) is statement part. Declarative part contains declarations of signals, components, functions etc. used in architecture. Statement part (also called code part) describes the function of the component. It contains internal signals assignments, connections between components used in architecture etc.
Everything will be clearer when I write an example. In previous post I wrote entity declaration for 2-input OR gate. Now it is time to create architecture body for this entity declaration:
architecture rtl of OrGate is begin y <= a or b; end architecture;
Line 1. – rtl is an architecture name and OrGate is an entity name. Architecture name should be simple and must be unique. This line associates architecture body with entity declaration.
Line 2. – word begin informs that declarations are finished and here starts code part.
Line 3. – created OR gate. Sign “<=” means assign right value to the left signal.
Line 4. – end of architecture body. You can do it in this way:
- end architecture;
- end architecture_name;
- end architecture architecture_name;
The architecture can be assigned to one entity, but single entity can be assigned to multiple architecture bodies. For example: 2-input OR and AND gates have the same input and output signals. So, the entity declaration can be the same. But architecture body will be different, because the functionality of these two gates is different.
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All source codes used in that post you can find on gitlab.com.
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