Testbench and Simulation

Having entity declaration and body architecture only one thing is still to do before compilation. I have to inform compiler which libraries are needed to analyze the design. Therefore, before entity declaration I inserted name of the library and package which will be used. This is ieee library and package std_logic_1164 (package, which contains declarations of basic types used in the design).

Full description of OR gate:

library ieee;
use ieee.std_logic_1164.all;

entity OrGate is
  port (	
    a	:in std_logic;
    b	:in std_logic;
    y	:out std_logic
end OrGate;

architecture rtl of OrGate is
  y <= a or b;
end architecture;


Testbench is an environment where can be tested functionality of the design. It is a component, written in VHDL (or Verilog etc…), but usually not synthesizable. In hierarchy it is a top level entity. It is created and used only for tests and verification. It checks if module (Unit Under Test) works correctly. In testbench, designer creates input vectors, sends these vectors to input ports of UUT and then observes the response at the output ports of UUT. I advise you to run simulation after every bigger change. It will help you to find much faster any bugs in the code, if there are any, of course.

Testbench code:

library ieee;
use ieee.std_logic_1164.all;

entity OrGate_tb is
end OrGate_tb;

architecture OrGate_tb_rtl of OrGate_tb is

  component OrGate is
    port (	
      a	:in std_logic;
      b	:in std_logic;
      y	:out std_logic
  end component;

  signal a_TB, b_TB 	:std_logic;
  signal y_TB 		:std_logic;

UUT: OrGate
  port map (
    a	=> a_TB,
    b	=> b_TB,
    y	=> y_TB

  a_TB <= '1', '0' after 100 ns, '1' after 300 ns;
  b_TB <= '0', '1' after 200 ns;

end OrGate_tb_rtl;


More or less you should be able to distinguish some parts of the code. Note that this testbench has no input or output ports. Everything happens inside. Testbench can be treated as external world.

Line 1. – these libraries are needed by compiler
Line 4. – entity declaration of testbench
Line 7. – architecture body of testbench
Line 9. – declaration of the component (OrGate) that will be instantiated. Component declaration is very similar to entity declaration of the module.
Line 17. – declarations of the signals (testbench level!)
Line 21. – Instantiated component: OrGate. Signals of the component are assigned to signals of the testbench. Here is created physically electrical connection. Testbench architecture doesn’t see signals inside the OrGate component, so signals can have the same names in both components. Look at direction of the arrows!
Line 28. – assigned test values to input signals of the OrGate module. Statement after changes value of the input vector after declared time.

Graphical presentation of the project:

Fig. 1


When you run simulation, program sets values on input signals, simulates behavior of the component (UUT) and then shows values on the outputs of it (in this case y output).

The results of simulation of OrGate are presented below. I used free Modelsim Altera Starter Edition to run the simulation.

Fig. 2


  1. Simulation is very important part of designing process. It allows you to check if design works correctly. Do not ignore it!
  2. Above is presented very simple testbench. Generally, the most important thing during testing, is to generate input vectors, which will verify UUT in as many cases as possible.

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All source codes used in that post you can find on gitlab.com.

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