Analysis

Files – data representation mismatch

by pwkolas
August 15, 2017December 31, 2019
Analysis

In previous post I explained in 5 steps how looks communication with files in VHDL. I presented some basic codes, which do simple write/read operations. Today I wanted to focus on that codes. If anyone tried to simulate them probably noticed that result are different from expectations. Below hopefully you will find an answer why…

by pwkolas
February 21, 2017December 22, 2019
Analysis, Keywords

Wait is very useful operation for simulation. It easily allows to simulate timing or signal dependencies. In next posts I am going to use it more often, so I wanted to give a short information about that statement.