Before you read that post, I encourage you to go through my two previous posts (here and here), which are about working with files. They describe basic approach and explain why that method is not recommended. Instead of this, in the following post I am proposing more standard, popular and convenient way to work with files in the VHDL.

TextIO is a package created to simplify working with files. It works in the same way on every operating system with almost every type available in the VHDL.

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Edge detector

Very often is necessary to detect edges of signals in designs. It can be helpful during developing communication interfaces, filters, sequential events. It seems that writing this module is easy, but as always designer should be careful. He has to remember, that his VHDL code will be synthesized to hardware, so he should keep in mind what structure will be created and how tools will understand his intentions.

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Registers (synchronous designs)

In previous posts I showed, how to build OR gate. This was an example of combinational logic. If you look at the code, you will see, that output depends only on present inputs and changes as fast as possible after modifying them. Though you have to know how to build combinational logic and how it works, you won’t create any bigger design only with that. To store data or pipeline the calculations, you have to create synchronous logic, dependent on a clock.

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Testbench and Simulation

Having entity declaration and body architecture only one thing is still to do before compilation. I have to inform compiler which libraries are needed to analyze the design. Therefore, before entity declaration I inserted name of the library and package which will be used. This is ieee library and package std_logic_1164 (package, which contains declarations of basic types used in the design).

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