Next step in extending test automation is to create model of the filter and run some tests on it. Perfect applications which will do that job are environments for technical and mathematical computations like Matlab or Octave, which very easily allow to express even complex algorithms.
Read More »Developing design: moving average filter. Part 5 – model of the filter.At this moment I have a very simple testbench to test the filter. I created a short test vector which checks calculations in the filter, but in very narrow range and only for 10 input samples. It really does not check much at all.
Below is depicted an actual method of testing:
It contains only an UUT, a short input vector, and output data which must be checked manually. Not much. Can I be sure that UUT will be tested in all corners? No.
Read More »Developing design: moving average filter. Part 4 – automatization of tests – idea.In previous posts I specified how filter should work and I described it in VHDL. Now it came time to test our filter. Below you can find very basic testbench:
Read More »Developing design: moving average filter. Part 3 – testbench.I created for filter basic and simple requirements:
Below you can find the code of the filter:
Read More »Developing design: moving average filter. Part 2 – filter.I wanted to briefly describe main steps which should be taken to correctly implement designs in VHDL (but of course it works for any other languages). As an example I chose simple moving average filter. The purpose is not to build something difficult, but to show how to build working, well-tested designs.
What are these steps?
Read More »Developing design: moving average filter. Part 1 – introduction.Wait is very useful operation for simulation. It easily allows to simulate timing or signal dependencies. In next posts I am going to use it more often, so I wanted to give a short information about that statement.
Read More »WaitIf you have a hierarchical design (so one block is built from others), you will have to instantiate and connect modules. Even if you have only one module and testbench dedicated for it, you will have to do that. In testbench used in previous post, I showed, how to instantiate a component, but there are more simpler ways to do that. Below you can find a few methods.
Read More »ComponentGeneric is a basic and very useful function of the VHDL. It allows creating more flexible and easy to modify components. Proper use of it will save your time and make your code clearer and more readable.
Read More »GenericVery often is necessary to detect edges of signals in designs. It can be helpful during developing communication interfaces, filters, sequential events. It seems that writing this module is easy, but as always designer should be careful. He has to remember, that his VHDL code will be synthesized to hardware, so he should keep in mind what structure will be created and how tools will understand his intentions.
Read More »Edge detectorIn previous posts I showed, how to build OR gate. This was an example of combinational logic. If you look at the code, you will see, that output depends only on present inputs and changes as fast as possible after modifying them. Though you have to know how to build combinational logic and how it works, you won’t create any bigger design only with that. To store data or pipeline the calculations, you have to create synchronous logic, dependent on a clock.
Read More »Registers (synchronous designs)