Testbench and Simulation

Having entity declaration and body architecture only one thing is still to do before compilation. I have to inform compiler which libraries are needed to analyze the design. Therefore, before entity declaration I inserted name of the library and package which will be used. This is ieee library and package std_logic_1164 (package, which contains declarations of basic types used in the design).

Read More »Testbench and Simulation

Architecture body

In previous post I presented entity declaration and gave simple example. Now it is time for second part – architecture body. Without this part, you won’t be able to create any module in VHDL.

Entity declaration gives information how module is connected with external world. Architecture body gives information what is inside of the module. It specifies relationship between input and output ports. In other words it specifies behavior of the module.

You should know there are three different modeling styles which allow to describe architecture body:

  • structural description
  • behavioral description
  • dataflow description

Sometimes some people add the fourth style – mixed, which is combination of three mentioned styles.

Read More »Architecture body

About VHDL…

All about history, advantages and disadvantages of VHDL you can find on wiki or other similar sites, so there is no point in copying this information. Here I would like only to list main features of this language:

Read More »About VHDL…