If you have a hierarchical design (so one block is built from others), you will have to instantiate and connect modules. Even if you have only one module and testbench dedicated for it, you will have to do that. In testbench used in previous post, I showed, how to instantiate a component, but there are more simpler ways to do that. Below you can find a few methods.

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Testbench and Simulation

Having entity declaration and body architecture only one thing is still to do before compilation. I have to inform compiler which libraries are needed to analyze the design. Therefore, before entity declaration I inserted name of the library and package which will be used. This is ieee library and package std_logic_1164 (package, which contains declarations of basic types used in the design).

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Entity declaration

As mentioned in previous post, systems are created using one or more entities. In case of many entities in the project, the uppermost level of it, is top-level entity. To connect modules with other modules or external world, ports and signals are used (Fig. 1). Main role of entity declaration is to define these ports – their names, types, width and direction. Basically entity declaration shows how module is seen by other modules. It describes the external view of the module with no information what is inside. Additionally entity declaration includes name of the entity and other parameters (constants, types, asserts, function etc).

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About VHDL…

All about history, advantages and disadvantages of VHDL you can find on wiki or other similar sites, so there is no point in copying this information. Here I would like only to list main features of this language:

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