Recently I had to implement square root algorithm in an FPGA. During research I found quite old, but interesting article: “A New Non-Restoring Square Root Algorithm and Its VLSI Implementations” written by Yamin Li and Wanming Chu. For educational purposes I decided to implement presented algoritm in VHDL.Read More »Square Root. Part 1 – iterative version.
I don’t like magic numbers or redundant variables in the code. They make it unclear and unreadable. Fortunately, VHDL gives many various options to eliminate such parts. One of them are predefined attributes. VHDL delivers many groups of attributes, which are useful in many situations. Some of them work only with signals, other with specific data types etc., but in general, rule of using an attribute is always the same:
object‘attributeRead More »Attribute LENGTH
I created for filter basic and simple requirements:
- average of 4 samples
- signal enable:
- ‘1’ – filter ON
- ‘0’ – filter OFF, zeros at the output
- synchronous reset
- don’t care about frequency, resources etc.
- output value updated in every cycle
Below you can find the code of the filter:Read More »Developing design: moving average filter. Part 2 – filter.