Simulation

Developing design: moving average filter. Part 7 (last) – testbench.

This is the last part about creating almost automatic testbench for Moving Average Filter. In the previous post I presented blocks for reading and writing. Now it is time to connect all blocks to each other in the main testbench. Testbench contains three blocks:

  • block which reads data from external file,
  • filter,
  • block which writes output data to external file.

Testbench additionally contains clock generation and other processes which drive control and testbench signals.

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Developing design: moving average filter. Part 6 – reading and writing to the files.

I had a break in developing filter (last part is here), but before doing next steps, I had to make a short introduction to working with files in VHDL. You can read about it here, here and here. Now I am going to use that knowledge and move on with the filter. In the last part I implemented the filter in Octave, generated test vectors, sent them through the filter and wrote all data to files.

Now it is time to start building testbench, where the filter could be easily and automatically verified with different test vectors. To achieve it, testbench has to read data from a file and pass it to the filter and then, write output values from the filter to another file.

Read More »Developing design: moving average filter. Part 6 – reading and writing to the files.

Developing design: moving average filter. Part 5 – model of the filter.

Next step in extending test automation is to create model of the filter and run some tests on it. Perfect applications which will do that job are environments for technical and mathematical computations like Matlab or Octave, which very easily allow to express even complex algorithms.

Read More »Developing design: moving average filter. Part 5 – model of the filter.

Developing design: moving average filter. Part 4 – automatization of tests – idea.

At this moment I have a very simple testbench to test the filter. I created a short test vector which checks calculations in the filter, but in very narrow range and only for 10 input samples. It really does not check much at all.

Below is depicted an actual method of testing:

AutmaticTesting1
Fig. 1

It contains only an UUT,  a short input vector, and output data which must be checked manually. Not much. Can I be sure that UUT will be tested in all corners? No.

Read More »Developing design: moving average filter. Part 4 – automatization of tests – idea.

Wait

Wait is very useful operation for simulation. It easily allows to simulate timing or signal dependencies. In next posts I am going to use it more often, so I wanted to give a short information about that statement.

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Testbench and Simulation

Having entity declaration and body architecture only one thing is still to do before compilation. I have to inform compiler which libraries are needed to analyze the design. Therefore, before entity declaration I inserted name of the library and package which will be used. This is ieee library and package std_logic_1164 (package, which contains declarations of basic types used in the design).

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