Developing design: moving average filter. Part 7 (last) – testbench.

This is the last part about creating almost automatic testbench for Moving Average Filter. In the previous post I presented blocks for reading and writing. Now it is time to connect all blocks to each other in the main testbench. Testbench contains three blocks:

  • block which reads data from external file,
  • filter,
  • block which writes output data to external file.

Testbench additionally contains clock generation and other processes which drive control and testbench signals.

Read More »Developing design: moving average filter. Part 7 (last) – testbench.

Developing design: moving average filter. Part 6 – reading and writing to the files.

I had a break in developing filter (last part is here), but before doing next steps, I had to make a short introduction to working with files in VHDL. You can read about it herehere and here. Now I am going to use that knowledge and move on with the filter. In the last part I implemented the filter in Octave, generated test vectors, sent them through the filter and wrote all data to files.

Now it is time to start building testbench, where the filter could be easily and automatically verified with different test vectors. To achieve it, testbench has to read data from a file and pass it to the filter and then, write output values from the filter to another file.

Read More »Developing design: moving average filter. Part 6 – reading and writing to the files.


Before you read that post, I encourage you to go through my two previous posts (here and here), which are about working with files. They describe basic approach and explain why that method is not recommended. Instead of this, in the following post I am proposing more standard, popular and convenient way to work with files in the VHDL.

TextIO is a package created to simplify working with files. It works in the same way on every operating system with almost every type available in the VHDL.

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Files – theory & examples

VHDL provides mechanism to work with files. This feature is useful, when there is a need to store some data like test vectors, parameters or results of the simulation. Way of working with files in VHDL is very similar to other languages. File is treated as an object. It can be created in an architecture body, process or subprograms. To properly work with files, following steps should be done:

1. Define type of a file
2. Declare object of the defined file type
3. Open the file
4. Perform write/read operations
5. Close the file

Read More »Files – theory & examples